Realization of 64-Bit MAC Units using Modified Wallace Structure

Authors:SREENIVASULU GADDE, V.MADHURI

1140-1143

An FPGA Implementation of Real-Time Finger-Vein Recognition System for Security Levels

Authors:DURGA VEERA PRASAD.V, A.ARUNKUMAR GUDIVADA

1144-1149

Design of Low Power Reversible Decoder using CMOS Pass Transistor Logic

Authors:SHAIK RAFFIQ, T. GANGA PRASAD, DR. N. USHA RANI

1150-1153

Performance Analysis of Low Voltage Low Power Inverter Based Comparator using CMOS Technology

Authors:P. VEERA BRAHMAM REDDY, K.V.SATYANARAYANA

1154-1159

A High Performance Pulse Triggered Flip-Flop Design with Pulse Enhancement

Authors:K.VANI, B.VIJAY KUMAR

1160-1163

On Chip Network Design to Support Guaranteed Traffic Permutation in MPSOC Applications

Authors:K.DEVALAXMI, DR.S.BALAJI, P.NAVITHA

1164-1168

FPGA Implementation of the 2/3 LSB Steganography using DWT

Authors:J.RAJA KULLAYAPPA, K.S.M.MUSA MOHINUDDIN, C.MD.ASLAM

1169-1174

Design of 16 Bit Ladner Fischer Based Modified Carry Select Adder using D-Latch

Authors:P.DIVYA, M.PURNA SEKHAR

1175-1180

A Parallel Prefix Tree Based 64-Bit Comparator for High Speed and Low Power Operations

Authors:SAHITHI ADDEPALLI, MURALI MALIJEDDI

1181-1185

Implementation of High Performance Spanning Tree Adder using Quaternary Logic

Authors:GARNEPUDI SAI CHAND, S. PRABHU DAS

1186-1193